1. Field of the Invention
This invention relates to an improved hierarchical semiconductor digital chip design and method for implementing the design, and more particularly to a chip design that optimizes pin locations for internal timing of a functional block.
2. Description of Background
Designers of the physical embodiment a semiconductor chip to carry out a logic function traditionally divide the overall chip structure into functional blocks that are small components of the overall function. These functional blocks are treated as abstractions at the top level. The first level of abstracted blocks are further divided into yet smaller physical blocks that are themselves abstracted and this process of dividing into blocks and treating them as abstracts continues until at the lowest level the content of the physical block is a reasonable small enough portion of the of the logic so that people and or programs can work with it. FIG. 1 illustrates this hierarchical approach to the design of complex digital electronic components such as computer components. A functional block referred to here as a macro is comprised of standard semiconductor circuit elements lc commonly referred to as leaf cells. These macros are combined and interconnected (not shown) to form the overall chip structure unit.
The logical functions executed by the leaf cells that make up an abstract determine the need for terminals called pins associated with the abstract along with need for points that can be connected together to form a specific network. A typical prior art design is illustrated in FIG. 2. The enclosing rectangular frame is meant to represent the abstract. The abstract can be thought of as the bounding box of the logical block. Input pins and output pins are normally placed on the edge of the abstract as shown in the FIG. 2. Leaf cells A, B, C, and D formed in the semiconductor are connected to corresponding input pins A, C, and D (input pin A serves leaf cells A and B in this illustration) and output pins A, B, C, and D. These connection points to the leaf cells called pins are usually placed around the peripheral border of an abstract, usually on the side or corner or combination thereof that results in the shortest distance to the next pin in the same network in a manner similar to how one would construct a logical flow diagram. However, this prior art pin placement design can create a problem. The wiring paths among pins and the placement of leaf cells within an abstracted functional block may be critical to an efficient implementation of its logical function and if not considered can be critical to the success of the network. One of the problems encountered with the prior art pin placement design are the need for additional re-powering circuit and wire delay—the location of the pins has an effect on the circuit delays within the abstracted functional block. In FIG. 2 the small boxes labeled i represent re-powering circuits required because of the distance between the leaf cell lc and the input/output pins located on the border of the macro. For example, the re-power circuitry is comprised of a pair of serial connected inventors needed to drive the distance between the leaf cell driver and an output pin. Another problem is perimeter crowding—the perimeter of the physical abstracted functional block can limit the number of pins that can be placed.
For example, pin placement affects circuit delay when the input pin is on one side of an abstracted functional block and the output pin is on the opposite side. The physical distance between pins may be so great that additional buffering may be required to transmit the signal or form the logic, thereby introducing additional circuit delay. The prior art techniques do not consider information about the logic within the abstracted entity when placing pins, but merely the connection between the pin and the next level of the hierarchy. The additional delay within an abstracted functional block is a result not only of the addition of extra circuits to implement the this functional block, but also because metal that comprises the wiring between the pins and the circuits of the abstracted functional block often has a higher delay characteristic than a similar connection at the next level in the hierarchy. Hierarchical designs often allocate metal layers to each level of abstraction in the hierarchy such that the lowest level of hierarchy gets the metal layers with a larger resistance per unit length, resulting in a larger delay per unit length. Therefore, as a general rule, any distance that can be traversed across an abstracted functional block on a higher level of metal (usually available at the next level of the hierarchy) rather than at the lower level of the hierarchy will take less time.
For any given pin geometry a fixed number of pins will fit per unit length of the perimeter of the abstracted functional block. In some cases the abstract's perimeter is not long enough to contain the number of pins required by that abstract. In the prior art designs, the abstract's area is increased until its perimeter is sufficiently long to accommodate the number of pins required. But this increases the distance between pins and consequentially the delay among paths. In addition, there is a non-linear increase in abstract area with increase in perimeter length, taking up silicon space merely for the sake of pin placement.